| 标题 |
A Ring Router Microarchitecture for NoCs
相关领域
计算机科学
路由器
芯片上的网络
单臂路由器
并行计算
多核处理器
核心路由器
嵌入式系统
计算机网络
计算机体系结构
布线（电子设计自动化）
炸薯条
微体系结构
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AI链接 arxiv.org |
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| 其它 | Network-on-Chip (NoC) has become a popular choice for connecting a large number of processing cores in chip multiprocessor design. In a conventional NoC design, most of the area in the router is occupied by the buffers and the crossbar switch. These two components also consume the majority of the router's power. Much of the research in NoC has been based on the conventional router microarchitecture. We propose a novel router microarchitecture that treats the router itself as a small network of the ring topology. It eliminates the large crossbar switch in the conventional design. In addition, network latency is much reduced. Simulation and circuit synthesis show that the proposed microarchitecture can reduce the latency, area and power by 53%, 34% and 27%, respectively, compared to the conventional design. |
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研友_仲剑心 在
2020-10-06 22:03:39 发布，悬赏 10 积分
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