比较器
符号
CMOS芯片
计算机科学
偏压
带宽(计算)
功率(物理)
电子工程
算法
数学
电压
电气工程
工程类
算术
物理
电信
量子力学
作者
Martijn Timmermans,Kyle van Oosterhout,Marco Fattori,Pieter Harpe,Yao‐Hong Liu,Eugenio Cantatore
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2024-02-13
卷期号:59 (4): 1194-1203
标识
DOI:10.1109/jssc.2024.3352735
摘要
This work presents a power-efficient level crossing (LC) ADC designed to digitize sparse signals. It uses dynamically self-biased comparators, which require minimal current when the input voltage is far from a decision threshold. It also uses a DAC architecture which avoids the signal attenuation commonly present in prior LC ADC works, improving the achievable SNDR. The prototype is designed and implemented in a 65-nm CMOS technology, and occupies an area of 0.0045 mm2. In a 20 kHz bandwidth, the LC-ADC achieves a 64 dB SNDR. Thanks to the proposed techniques a power efficiency of up to 1.8 fJ/conv.-step is achieved for sinusoidal inputs. For sparse biopotential signals, a FoMW as low as 0.9 fJ/conv.-step was measured. This makes the prototype interesting for e.g., biomedical applications that make use of spike-based processing.
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