Electrical Fault Isolation for Functional and Logic Hard Failures using Laser Voltage Imaging

调试 计算机科学 扫描链 边界扫描 断层(地质) 故障检测与隔离 电子工程 工程类 集成电路 人工智能 操作系统 地质学 地震学 执行机构 程序设计语言
作者
Kan Sun,Silambarasan Karuppannan,Soon Woei Chong,Guofeng You,Wilson C. H. Lee,Lesly Endrinal
出处
期刊:Proceedings 卷期号:84437: 115-119 被引量:1
标识
DOI:10.31399/asm.cp.istfa2022p0115
摘要

Abstract Hard functional and logic failures which are insensitive to temperature, voltage, or frequency have become increasingly difficult to debug in advanced technology nodes, especially when Photon Emission (PEM) analysis could not provide any leads and Dynamic Laser Stimulation (DLS) could not be used due to the nature of the failure (no pass/fail margin). Laser Voltage Imaging (LVI), which is an extension of the Laser Voltage Probing (LVP) technique, provides a visual map of active components that are toggling at a certain frequency. This technique is widely employed in scan chain debug due to its simplicity, efficiency, and accuracy. However, most of LVI applications in literature reviews only involve scan chain fault isolation. This paper will present alternative applications for LVI, apart from scan chain debug. One specific application is the debug of a broken signal path by sending a periodic signal as a stimulus to a GPIO pad and tracing the LVI signal through the path by frequency mapping. In this paper, the concept and methodology behind this fault isolation approach will be discussed in full detail. Furthermore, three case studies of different types of hard failures with different applications of LVI will also be presented: an IO functional failure, an ATPG (Automatic test pattern generation) SAF (Stuck At Fault) failure and a BSDL(Boundary scan description language) input interconnect failure, to illustrate how LVI could be deployed in fault isolation for those functional and logic hard failures.

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