An analysis on the ambipolar current in Si double-gate tunnel FETs

This work presents a study on the influence of the design parameters on the ambipolar current (IAMB) of the Tunnel Field Effect Transistors (TFETs). Using numerical device simulations, IAMB is reduced progressively by underlapping the gate and the drain, by using low-k spacers and by placing the contacts in the top and bottom configuration. It is explained that a structure with top and bottom contacts leads to the field distribution inside the drain spacer, limiting the ambipolar current through the device. A TFET structure with ultra-low ambipolar current, totally independent of the gate voltage, is obtained by combining the layout of top and bottom contacts with low-k spacers. The scaling of the Silicon (Si) TFET is limited by the length of the drain spacer that cannot be scaled beyond a minimal limit without increasing IAMB to undesired high values.