Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing

Resistive crossbar array for in-memory computing suffers from high static power and sneak-path current. To address these issues, we proposed a ferroelectric Hf _x Zr _1−x O ₂ (HZO) based capacitive crossbar array for in-memory computing. The non-volatile capacitive synapse allows the minimization of both sneak-path current and steady-state power consumption. Furthermore, since the capacitive synapse is read at DC 0V, we claim that this architecture allows read-disturbance-free and energy-efficient in-memory computing. In this brief, we first introduce the device properties of the non-volatile capacitor and their underlying physical mechanism. Moving to array-level analysis, we obtain the optimal ratios between reference and ferroelectric capacitors ( $\text{C}_{\mathrm{ ref}}/\text{C}_{\mathrm{ FE}}$ ) for the maximum output swing to occur. Subsequently, the tradeoff between output swing and delay has been explored. We show that a $128\mathrm {\times }128$ non-volatile capacitive crossbar array can be designed with >75 mV swing and <30 ns delay. Under transient noise simulation, capacitive array is compatible with 3-bit partial sum quantization. Without steady-state energy consumption, the optimized capacitive array can achieve 3.8 pJ per vector-matrix multiplication, $14.3\mathrm {\times }\mathrm {\sim } 57.3\mathrm {\times }$ lower compared to those of the representative resistive crossbar arrays. Furthermore, we propose a charge-cancelling technique and a guideline with on/off ratio projection for a system with arbitrary ENOB requirements to address the issues caused by limited on/off ratios. Finally, we suggest a 1/3 $\text{V}_{\mathrm{ w}}$ scheme with little write disturbance.