绝缘体上的硅
CMOS芯片
材料科学
光电子学
辐射硬化
电子线路
MOSFET
电气工程
电子工程
晶体管
工程类
电压
硅
探测器
作者
A. Makihara,Tatsuya Yamaguchi,Y. Tsuchiya,T. Arimitsu,H. Asai,Yoshiya Iide,H. Shindou,S. Kuboyama,Sumio Matsuda
出处
期刊:IEEE Transactions on Nuclear Science
[Institute of Electrical and Electronics Engineers]
日期:2004-12-01
卷期号:51 (6): 3621-3625
被引量:13
标识
DOI:10.1109/tns.2004.839155
摘要
We evaluated single-event effects (SEEs) in test circuits fabricated at OKI with their 0.15 /spl mu/m Fully Depleted CMOS/SOI commercial process. The sample devices were designed with hardness-by design (HBD) methodology. The results are discussed for an effective hardening design associated with SEEs.
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