田口方法
材料科学
散热片
造型(装饰)
电子包装
焊接
复合材料
电子元件
热变形温度
有限元法
小型化
残余应力
包装工程
锡
机械工程
结构工程
冶金
工程类
艾氏冲击强度试验
极限抗拉强度
纳米技术
作者
De-Shau Huang,Wenbin Tu,Xiuming Zhang,Liang-Te Tsai,Ti-Yuan Wu,Ming-Tzer Lin
标识
DOI:10.1016/j.microrel.2016.07.006
摘要
Packaging technology developments in semiconductor chips are moving towards miniaturization, thinner products, lighter weights, and higher performance. However, in the process of packaging, warpage and residual stress have always been major problems, such as pin deviation, breakage, and weak signals. Further, the distinctive properties of the numerous materials that comprise a semiconductor chip demand different molding temperatures; thus, excessive internal thermal stresses are produced within the packaging structure which ultimately results in colloid warpage. This study used a 3D coordinate measuring machine to determine the levels of warpage produced in electronic packaging products and to verify the amount of warpage simulated by the finite element method. Then, Taguchi method was also utilized to analyze and discuss the four critical control factors namely: (1) shape of the heat sink; (2) thickness of molding; (3) molding temperature; and (4) thickness of soldering tin. Thus, the minimum thermal stress for electronic packaging components was obtained, which meant the optimal parameter combination for the packaging was a triangle-shaped heat sink, with a molding compound of 1.175 mm thick, a molding temperature of 170 °C, and a soldering tin that was 0.03 mm thick.
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