Design and formation of SiO₂/SiC interfaces with low interface state via phosphorus ions implantation in SiC power MOSFETs

This paper reports an effective approach to reduce the density of SiO 2 /SiC interface state (D it ), which can be applied in industry. Low energy implantation of phosphorus ions is carried on before high-temperature oxidation for reducing the D it near conduction band (E C ) edge. SiC MOSFETs formed by proposed oxidation process show lower on-state resistance and higher drain current density compared with normal process. The results of high-low frequency CV method reveal that D it near conduction band edge is 2.6×10 ¹¹ cm ^-2 eV ^-1 after P implantation while D it without P implantation is about 5.5×10 ¹¹ cm ^-2 eV ^-1 . Non-contact corona-Kelvin technique is used to test D it of SiO 2 /SiC interface. It reveals that it can be used to measure the D it at E C -0.05eV on whole wafer after oxidation and the results are sensitive to the surface roughness of interface.