A 14-bit 500-MS/s Pipelined-SAR ADC in 28-nm CMOS with Foreground and Background Calibration

A 14-bit 500-MS/s Pipelined-SAR (Successive Approximation Register) Analog-to-Digital Converter (ADC) in 2S-nm CMOS is presented in this paper. The ADC has two-stages. In the first stage, Multi-comparators are used to increase the speed of ADC. A foreground calibration method for capacitor mismatch and a background calibration method for gain mismatch are implemented. This design also optimizes the processing logic of the capacitor foreground calibration to increase the speed of the chip. In the second stage, two SAR ADCs basing on Time-Interleaved (TI) method are used to achieve the required sampling rate. The results reveal that the ADC achieves a 64.36 dB SNDR and 73.29 dB SFDR at 500-MS/s sampling rate without calibration, 66.19 dB SNDR and 83.50 dB SFDR at 500-MS/s sampling rate with calibration. The layout of core occupies 0.43 mm2 area and consumes 215.6 mW at 2.0/1.0 V supplies.