抖动
压控振荡器
电子工程
锁相环
计算机科学
CMOS芯片
相位噪声
双回路
探测器
循环(图论)
电气工程
工程类
电信
电压
数学
组合数学
作者
Chua‐Chin Wang,L. S. S. Pavan Kumar Chodisetti,Bo-Hao Liao,Pradyumna Vellanki,Tzung-Je Lee
标识
DOI:10.1016/j.mejo.2024.106355
摘要
A dual-loop CDR (Clock and Data Recovery) is presented to recover digital data from 1 to 6.5 Gbps. The presented frequency acquisition technique is based on full rate clock architecture. By utilizing modified Digital Quadri-correlator Frequency Detector (DQFD) and Frequency Increment/Decrement Control circuit, the lock-in range is improved. Furthermore, the issue of state loss during wide frequency range detection is successfully mitigated. The inclusion of two control wires in the Coarse-fine Tuning VCO enables the utilization of separate loop filters in the dual loops, resulting in a more effective reduction of noise and jitter. Utilizing a 40-nm CMOS process, the presented CDR design has been implemented. The post-layout simulation results at 6.5 Gbps shows a P2P and root-mean-square jitter values are 17.1 ps and 5.79 ps, respectively, for the retimed data.
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