TSPC Trigger-Based Testing Scheme for Pre-Bond Testing and Diagnosis of TSVs

TSVs are crucial components in enhancing the performance of three dimensional integrated circuits. Due to the limitations in current manufacturing technologies, various types of defects are prone to occur during the TSV fabrication process, significantly impacting the reliability of 3D ICs. In this paper, we present a TSPC trigger-based scheme for detecting TSVs during pre-bond testing, allowing for the detection and localization of various TSV faults. Through HSPICE simulation, the effectiveness of this testing scheme has been demonstrated under different process technologies. This method achieves high detection accuracy, low testing time, and minimal hardware overhead. Experimental results show that the detection accuracy of void defects can reach 400 ohms.