Analysis and Optimization Strategies Toward Reliable and High-Speed 6T Compute SRAM

In-SRAM Computation improves the throughput and energy-efficiency of data-intensive applications by utilizing parallelism and reducing the data transfers. However, when multiple wordlines are accessed simultaneously, a short-circuit path will likely incur dynamic read disturbance and generate extra direct current in 6T Compute SRAM (CSRAM). In order to mitigate this issue, existing works either degrade the access speed, use area-hungry bitcells, or incur architecture-level overheads. In this paper, we first perform a comprehensive circuit-level analysis of the dynamic read disturbance issues of 6T SRAM for the first time and find that such disturbance can be efficiently avoided by maintaining the bitline voltage at a high level. Second, we propose a novel energy-efficient, reconfigurable sense amplifier design that is able to achieve fast and reliable sensing when the bitline voltage level is high for the compute access. Third, we propose an adaptive wordline control scheme that keeps the bitline voltage at a high level to eliminate the dynamic read disturbance and the sneaky direct current pathway. Both the new sense amplifier and adaptive wordline control are also optimized to support the normal read access efficiently. We have validated our design in a 55nm CMOS technology. Experimental results show that our design not only reliably addresses the read disturbance and the extra direct current, but also operates 19% faster than the state-of-the-art design using an advanced 28nm FDSOI technology.