Breakdown Mechanisms of Power Semiconductor Devices

This paper reviews the physical breakdown mechanisms of Si-, SiC- and GaN-based power semiconductor devices. In the off-state in which Si-based Lateral Double-diffused MOS (LDMOS), SiC-based Schottky Barrier Diode (SBD), the PN junction and gate Schottky junction are reverse-biased, avalanche breakdown is responsible for the breakdown. For AlGaN/GaN high electron mobility transistors (HEMTs), due to the absence of a PN junction, there exist four breakdown mechanisms: (i) the high gate-leakage-current components, either through the surface-hopping conduction mechanism or through the vertical Schottky barrier, (ii) the impact-ionization-induced Schottky junction avalanche breakdown, whose positive temperature dependence of the breakdown voltage is a typical signature, (iii) the source–drain leakage current through the GaN buffer, owing to poor confinement and high N-type doping, and (iv) vertical breakdown, which can be particularly pronounced when AlGaN/GaN HEMTs are grown on an Si substrate. Avalanche breakdown and GaN buffer-leakage-current-induced breakdown are deeply investigated. Through Integrated Systems Engineering (ISE) simulation, the effects of the breakdown voltage on different GaN buffer layer concentrations and thicknesses were obtained. Finally, novel AlGaN/GaN HEMTs with a partially etched AlGaN layer have been fabricated. The test curves indicate that avalanche breakdown governs the breakdown when the GaN buffer layer is lightly N-type doped and thinner. The paper provides a reference in designing and achieving AlGaN/GaN HEMTs with high breakdown voltages.