Spur Reduction Circuit for Fractional-N PLLs

Fractional and reference spurs appear at the output of a fractional PLL along with the carrier. In the proposed architecture, two PLLs are conjunctly implemented for spur reduction—one fractional and other integer—with their control voltages summed together for dual control. A very low value (1/100) of the fractional frequency division ratio is considered. A fractional sampler is introduced that places bandstop notches at very low frequencies and hence, loop bandwidth of the fractional PLL has to be lower than the first spur frequency. To alleviate the issue of high area requirement by the second-order loop filter capacitors in the fractional PLL, the charge pump is divided into two parts with high and low values of pump currents. The charge pump with the low pump current drives the loop filter network segment with the resistor; thus, the area of the capacitor in this network can be reduced. By simulation in 180 nm CMOS technology, it is observed that the largest fractional spurs are reduced from $$+19.2$$ + 19.2 to $$-66.2$$ - 66.2 dBc, and the reference spurs from $$-28.5$$ - 28.5 to $$-67.8$$ - 67.8 dBc. Monte Carlo simulations show best and worst case spurs at $$-73$$ - 73 and $$-69$$ - 69 dBc, respectively. The architecture shows the phase noise characteristics of the integer PLL when identical oscillators are used in both the loops.