放大器
CMOS芯片
宽带
电气工程
电子工程
变压器
计算机科学
工程类
电压
作者
Bong-Jun Yang,Huizhen Jenny Qian,Tianyi Wang,Xun Luo
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2023-02-01
卷期号:58 (2): 357-370
被引量:11
标识
DOI:10.1109/jssc.2022.3191975
摘要
In this article, a wideband watt-level digital power amplifier (DPA) with high efficiency and large dynamic range is presented in CMOS technology for wireless applications. To achieve high output power with enhanced operation bandwidth (BW), the wideband matching network based on a reconfigurable power-combining transformer is used. Meanwhile, the $L$ – $C$ circuit is used to suppress the harmonics, which further improves the output power of the fundamental signal. In addition, the LO leakage is suppressed by the 12-bit power digital-to-analog converter (power DAC), which leads to high dynamic range of the proposed DPA. To verify the mechanism, a 1.2–3.6-GHz watt-level 12-bit polar DPA is implemented and fabricated using a conventional 40-nm CMOS technology. With 1.1-/2.5-V supply, the fabricated DPA exhibits peak output power ( $P_{\text {out}}$ ) of 32.67 dBm, peak drain efficiency (DE) of 45.1%, and peak power-added efficiency (PAE) of 35.5% at 2 GHz. It supports 50-MSyms/s 256-QAM with average output power ( $P_{\text {avg}}$ ) of 22.76 dBm, error vector magnitude (EVM) of −31.46 dB, and adjacent channel leakage ratio (ACLR) of −30.67 dBc, 10-MSyms/s 1024-QAM with $P_{\text {avg}}$ of 25.54 dBm, EVM of −38.2 dB, and ACLR of −38.71 dBc, and 5-MSym/s 4096-QAM with $P_{\text {avg}}$ of 22.97 dBm, EVM of −43.0 dB, and ACLR of −46.32 dBc, respectively.
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