Analysis and Mitigation of Negative Differential Resistance effects in Double-Gate Silicon-on-Insulator Negative Capacitance Field Effect Transistor with improved analog performance

Negative Capacitance Field Effect Transistors (NCFETs) offer the possibility of enhancing channel length scalability, with a key challenge being to ensure hysteresis and Negative Differential Resistance (NDR) free behavior. In this context, through TCAD-based simulations, for a symmetric Double-gate Silicon-on-Insulator (DG-SOI) baseline architecture with a Metal–Ferroelectric–Insulator–Semiconductor (MFIS) configuration, we first examine the root cause of NDR as being the FE layer with a small number of strongly coupled domains, which allows the drain to lower the surface potential (ΨSs) and internal gate voltage (Vint) on the source side. With this understanding of NDR, the inclusion of a paraelectric (PE) layer on the drain side of the gate stack, by splitting the stack into two halves laterally, while keeping the thickness of the stack unchanged, minimizes the drain's influence on the source-sided electrostatics. This results in the mitigation of NDR effects along with superior analog performance parameters, thus making these FE–PE gate stack-based NCFET devices suitable for analog circuit applications.