Nanoscale Size Control of Si Pyramid Texture for Perovskite/Si Tandem Solar Cells Enabling Solution‐Based Perovskite Top‐Cell Fabrication and Improved Si Bottom‐Cell Response

Abstract A monolithic perovskite/silicon tandem solar cell architecture is employed to surpass the single‐junction efficiency limit. Recently, there is an increasing need for the double‐sided textures in the Si bottom cell to be compatible with the solution‐processed perovskite top cell from an industrial perspective. Herein, a silver‐assisted alkaline etching method is applied to fabricate nanoscale Si pyramid textures, and the influence of varying pyramid size (400–900 nm) on the interface morphology and the performance of perovskite/Si tandem cells is investigated. It is demonstrated that electrical shunting starts to increase, and the open‐circuit voltage ( V OC ) decreases when the texture size exceeds the perovskite thickness (~500nm) due to the non‐uniform top‐cell formation on a rough Si surface. However, when the texture size is reduced to 400–500 nm, all spin‐coated perovskite top‐cell component layers exhibit an even form over the nanopyramid Si, resulting in a high V OC and an enhanced Si bottom cell current (≈1.0 mA cm −2 ) due to the suppressed reflectance at the top/bottom cell interface without using optical couplers. The double‐sided nanopyramid Si texture offers opportunities to increase tandem cell efficiency while reducing its production cost compared with the commonly used single‐sided textured Si.