A Low Noise High Speed Dynamic Comparator Insensitive to PVT and Common-mode Input

This paper proposes a PVT and input common-mode voltage insensitive dynamic comparator for high speed and high resolution SAR ADCs. In its dynamic preamplifier, a switched capacitor charge pump, instead of NMOS switch, is used to bias the input pair to prevent performance deterioration caused by PVT and input common-mode voltage variation, and a NMOS cross-coupled load based on dynamic bias is added on the output nodes to accelerate differential settling. In addition, the discharging switch and timing are carefully designed to balance speed and noise. The comparator circuit with above techniques has been verified in a 55nm CMOS process at 1GS/s. The simulation results show that the noise of the comparator is 194$\mu {\mathrm{V}}$ and the CLK-OUT delay is 152ps when input common-mode voltage equals 0.5V and the difference of the input signal equals 0.3mV. The proposed comparator also has good robustness to PVT variation, and the noise reaches 202$\mu {\mathrm{V}}$ and CLK-OUT delay reaches 211ps in the worst case respectively.