Design for Testability of Low Dropout Regulators

Integrated LDOs are closed loop systems; characterization of their gain and bandwidth is critical. Generally, gain and bandwidth parameters are extracted from LDO design simulations. However, LDO loop parameter testing requires breaking the loop and injecting a test signal into the IC. This paper presents test bed simulations and new test techniques for direct on-chip vectorless measurement of LDO DC loop gain and bandwidth. The LDO can be easily configured into two different test modes to measure these parameters. In test mode I, an additional op-amp is used as an integrator and is connected to the LDO control loop in a feedback servo loop. This forces a null at the LDO error amplifier input and simplifies DC gain measurements. The second amplifier stabilizes the DC operating point of the LDO pass transistor and error amplifier when the control loop is broken. Maintaining and controlling normal DC operating conditions is essential when measuring control loop parameters. Initial simulation results show that this approach maintains LDO component DC operating points and the LDO DC loop gain is measured with high accuracy. In test mode II, the LDO core is configured as an oscillator. The oscillation frequency can be used to estimate the bandwidth of the LDO and can be evaluated to monitor component faults. The Design for testability (DFT) technique to configure the LDO into these test modes is presented and the related practical problems and limitations are discussed.This new test technique has been applied to measure a working LDO test IC developed in a 65nm CMOS UMC technology. The simulation and practical implementation results show close agreement and the proposed test techniques can be practically integrated in a BIST structure.