倒装芯片
可靠性(半导体)
分层(地质)
材料科学
炸薯条
压力(语言学)
互连
造型(装饰)
芯片级封装
电子工程
集成电路封装
计算机科学
复合材料
电气工程
工程类
电信
物理
古生物学
功率(物理)
语言学
胶粘剂
哲学
图层(电子)
量子力学
生物
俯冲
构造学
作者
In Hak Baick,Moon Soo Lee,Minwoo Lee,Byungwook Kim,Sang Su Ha,Seong Won Jeong,Min Kim,Sangwoo Pae
标识
DOI:10.1109/iirw.2017.8361230
摘要
Epoxy molding compounds (EMC) are commonly applied to mitigate the thermo-mechanical reliability issue associated with the chip-to-package interaction (CPI) of LK/ULK applied flip chip packages. To understand the effect of EMC viscoelastic properties on the stress level induced on the bump, under bump and chip edge interconnects, a series of numerical simulations and reliability test using CPI test vehicles (TV) are carried out using 28/14/10nm process. The results showed that the higher storage modulus leads to lower stress level at the near bump and under bump interconnect layers, and enhanced CPI reliability. An improved approach based on phase lag (tan δ) value and stress relaxation is proposed to evaluate the performance of EMC materials. Our CPI TV thermo-mechanical test results shows good agreement to our newly proposed guide line. Additionally, we show that high modulus induced EMC/SR delamination can be effectively eliminated by increasing SR thickness.
科研通智能强力驱动
Strongly Powered by AbleSci AI