与非门
闪光灯(摄影)
可靠性(半导体)
计算机科学
闪存
计算机数据存储
低密度奇偶校验码
计算机硬件
电子工程
逻辑门
解码方法
算法
工程类
物理
光学
量子力学
功率(物理)
作者
Xiaotong Fang,Meng Zhang,Yifan Guo,Fei Chen,Binglu Chen,Xuepeng Zhan,Jixuan Wu,Fei Wu,Jiezhi Chen
标识
DOI:10.1109/tcad.2023.3240932
摘要
3-D NAND flash memory is the ubiquitous nonvolatile memory (NVM) on the market because of its large storage capacities, high reliability, and low bit cost. The reliability characteristics of 3-D NAND flash memory, however, are considerably different from those of 2-D NAND flash memory due to the peculiar architectures. In this article, read disturb (RD) at various program/erase (P/E) stages is thoroughly explored. To adjust the low-density parity check (LDPC) codes dynamically and extend the lifetime of 3-D NAND flash memory, short-term lifetime prediction models of RD and endurance are proposed based on in-depth studies on the correlations of fail bit count (FBC) at various lifetime stages, and their accuracy is tested experimentally. A new short-term warning system (STWS) is proposed to extend the lifetime of 3-D NAND-based storages. It consists of the error-bits’ prediction module (EBPM) and the self-adjustable LDPC codes module (SLDPC), where EBPM predicts FBC periodically and SLDPC preallocates LDPC codes for future use based on the result of EBPM. The experimental result shows that our prediction models have high reliability, and STWS can effectively prolong the lifetime of NAND flash. The findings of this study provide fundamental insights into FBC degradation in 3-D NAND flash, as well as a simple and practical method for building 3-D NAND-based storage with high reliability.
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