A High-Speed and Fully Symmetric Time-to-Digital Converter with Picosecond Resolution

This paper presents the design of a high-resolution time-to-digital converter (TDC) which uses a fully symmetric sense-amplifier-based flip-flop (SAFF) with improved delay chains. Simulation results show that the proposed flip-flop has a small metastability window compared with the other SAFFs. Additionally, the delay and the power are smaller. A high-speed Vernier TDC is also proposed with time resolution of 2. 5ps based on the novel SAFF.