Design of a 10 Bit Low Power Split Capacitor Array SAR ADC

In this paper, a low power split capacitor array structure based successive approximation register (SAR) type analog to digital converter (ADC) is proposed. To minimize power, this ADC combines the capacitive digital to analog converter (DAC) with the sample and hold (S/H) circuit, uses the Split binary-weighted capacitor array for the DAC, and utilizes the open-loop comparator. The ADC consumes low power with good performance. The DAC efficiently uses charge recycling to achieve a high speed of operation. The proposed ADC is designed using 0.18-μm CMOS technology. At a 1.8-V supply and 2 MS/s, the ADC achieves a spurious-free dynamic range (SFDR) of 54 dB and consumes 0.27633 mW.