CMOS芯片
可靠性(半导体)
工作(物理)
功能(生物学)
工作职能
可靠性工程
电子工程
计算机科学
材料科学
工程类
金属
机械工程
物理
冶金
功率(物理)
量子力学
进化生物学
生物
作者
J. Franco,Hiroaki Arimura,S. Brus,E. Dentoni Litta,Kristof Croes,N. Horiguchi,B. Kaczer
标识
DOI:10.1016/j.sse.2024.108929
摘要
Multi-Vth CMOS device technologies have become standard for System-on-Chip designs. In Replacement Gate technologies, distinct device Vth's are achieved by deploying different work function metal stacks, and thus concerns exist about the possible chemical interaction of different gate metals with the underlying dielectrics potentially affecting the device performance and reliability. We present a comprehensive study, comprising both electrical measurements and simulations, carried out on a planar transistor platform with state-of-the-art gate stacks. Two different metal stacks are deployed to fabricate low-Vth and ultra-high Vth pMOS and nMOS device flavors. The study provides fundamental insights on the impact of TiAl-based gate metal on EOT, gate leakage, interface quality, carrier mobility, short channel performance, PBTI and NBTI reliability.
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