SADP etch process development using PR core for sub 17nm DRAM

Self-aligned double patterning (SADP) process has become the standard patterning technology for extending the half-pitch resolution beyond current ArF lithography tool's limit. In this paper, we mitigate the compressive stress of ALD SiO2 spacer in SADP etching and solve the SADP spacer pattern collapse problem to minimize the pitch walking deviation. The SADP technology is applied for 17nm of buried word line (bWL) process to meet DRAM scaling requirements.