Triple-Tail Common-Mode Insensitive High-Speed Dynamic Comparator for Analog In-Memory Computing Architectures

Analog in-memory computing architectures demand high-speed analog-to-digital converters, for which a dynamic comparator is a crucial building block. Speed and common-mode insensitivity are the critical features of such dynamic comparators. Most of the reported dynamic comparators achieve high speed only for a narrow range of the input common-mode voltages. The comparators' performance degrades at the extremities of common-mode voltages. We propose a common-mode insensitive cascode cross-coupled dynamic comparator to overcome this drawback. The proposed comparator is designed, simulated, and compared with the state-of-the-art techniques in a 65 nm CMOS technology. At 1.1 V supply voltage, the proposed comparator shows a delay of 37 ps when the input difference is 10mV with a common-mode voltage of 400mV.