Novel forksheet device architecture as ultimate logic scaling device towards 2nm

To compensate for expected gate pitch scaling slowdown below 42nm, several scaling boosters are needed to reduce the logic standard cell height (CH). However, limited scaling benefits can be achieved using FinFET and Gate all around (GAA) nanosheets (NSHs) due integration limits in achieving tight PMOS to NMOS (PN) separation. Therefore, a novel forksheet (FSH) device architecture is proposed achieving extremely scaled PN space using limited additional processing complexity. The FSH achieves 10% frequency increase at iso-power and 24% power reduction at iso-frequency compared to GAA nanosheet with a combined area scaling of 20%. SRAM bit cell area scaling of 30% and read delay performance increase is shown.