Novel Carrier Measurement Methodology for Floating Gate of Sub-20 nm Node Flash Memory Using Scanning Nonlinear Dielectric Microscopy

Abstract The transistor structure of memory devices and other cutting-edge semiconductor devices has become extremely minute and complicated owing primarily to advances in process technology and employment of three-dimensional structures. Among the various approaches to improve the device performance and functionality, optimizing the carrier distribution is considered to be quite effective. This study focuses on scanning nonlinear dielectric microscopy (SNDM), a capacitance-based scanning probe microscopy technique. First, to evaluate SNDM's potential for high-resolution measurement, the most commonly used metal coated tip with a tip radius of 25 nm was used to measure a quite low-density impurity distribution. Then, after confirming that the SNDM's S/N ratio was sufficiently high for the smaller probe tip, an ultra-fine diamond probe tip with a nominal tip radius of lesser than 5nm as an SNDM probe tip to measure sub-20 nm node flash memory cell transistors was employed. Successful results were obtained and are reported.