An efficient ROM compression technique for linear- interpolated direct digital frequency synthesizer

A direct digital frequency synthesizer (DDFS) based on piecewise linear approximation method is presented in this paper. The proposed method allows sequential read access to memory cells per one clock cycle using time sharing. The output values will be momentarily stowed and read at a later time; thereby the slope is simply derived from these sinusoid points at successive phase angles. As a consequence, the DDFS only needs to store fewer coefficients and the hardware complexity is significantly shortened. The proposed DDFS has been analyzed using MATLAB Simulink and examined over entire Nyquist frequency band. The simulation results show a promising result of 84 dBc spurious free dynamic range (SFDR). The resultant low complexity architecture along with high spectral purity synthesized signal meets the specifications of recent portable battery-driven products.