电容器
逐次逼近ADC
比较器
电容
炸薯条
电子工程
校准
线性
偏移量(计算机科学)
电阻器
物理
电气工程
计算机科学
工程类
电压
电极
量子力学
程序设计语言
作者
Masato Yoshioka,Kiyoshi Ishikawa,Takeshi Takayama,Sanroku Tsukamoto
标识
DOI:10.1109/tbcas.2010.2081362
摘要
This 10-b 50-MSamples/s SAR analog-to-digital converter (ADC) features on-chip digital calibration techniques, comparator offset cancellation, a capacitor digital-to-analog converter (CDAC) linearity calibration, and internal clock control to compensate for PVT variations. A split-CDAC reduces the exponential increase in the number of unit capacitors needed and enables the input load capacitance to be as small as the kT/C noise restriction. The prototype fabricated in 65 nm 1P7M complementary metal-oxide semiconductor with MIM capacitor achieves 56.6 dB SNDR at 50-MSamples/s, 25-MHz input frequency and consumes 820 μW from a 1.0-V supply, including the digital calibration circuits. The figure of merit was 29.7 fJ/conversion-step under the Nyquist condition. The ADC occupied an active area of 0.039 mm(2) .
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