Parametric Study on the Void Risk in FC-POP Molded Underfill Process Using a Novel Porous Media, Two-Phase, Compressible Flow Simulation Method

倒装芯片 空隙(复合材料) 材料科学 球栅阵列 多孔性 机械工程 复合材料 焊接 工程类 胶粘剂 图层(电子)
作者
Moon Soo Lee,Inhak Baick,Min Suk Jeong,Min Gyu Kim,Seo Hyun Kwon,Myeong Soo Yeo,Hwasung Rhee,Sangwoo Pae
出处
期刊:IEEE Transactions on Device and Materials Reliability [Institute of Electrical and Electronics Engineers]
卷期号:20 (2): 286-292 被引量:3
标识
DOI:10.1109/tdmr.2020.2985209
摘要

Molded underfill process provides many benefits for higher productivity and lower cost over the conventional capillary underfill process. However, the void defects in a molded underfill process could cause pop-corning effect and solder extrusion during the reflow process. This paper presents a highly efficient and accurate hybrid model that can be applied to diagnose the void risk in vacuum molded underfill processes of real flip-chip, package-on-package devices with complex ball arrays and large PCB strips. The model combines multi-zone porous media model, Hele-Shaw model and compressible two-phase computational fluid dynamics model. The model has been well validated in terms of the entrapped void size and its behavior with flow visualization experiments. Also, a set of parametric studies on a FC-POP molded underfill flow process were performed to pre-assess the future node's molded underfill process. Not only the model provides a better understanding of the physics of void entrapment but also it is proven to be an effective tool for assessing the potential void risk through its application to 10nm flip-chip, package-on-package device manufactured in mass production line.
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