Low Power Design of a MIPI Digital D-PHY for the Mobile Signal Interface

In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using CMOS process under 1.2V supply.