Track & Hold Amplifier Investigation for 100-GHz Bandwidth, 200-GS/s ADC Front Ends

We report on the track and hold amplifier (THA) topology choice and design details of a $4\times $ time-interleaved 200-GS/s SiGe BiCMOS ADC front end with a measured SNDR > 25 dB up to 63 GHz, and with a large signal bandwidth of 58 GHz when subsampling at 5 GS/s. We show that by replacing the current-mode-logic (CML) MOS switch with a quasi-CML switch and increasing the tail current, a THA with a measured small-signal bandwidth of 101 GHz is obtained in the same 55-nm SiGe BiCMOS technology. The ADC front end bandwidth could thus be further improved at the same sampling rate.