A 53.6-to-60.2GHz Many-Core Fundamental Oscillator With Scalable Mesh Topology Achieving -136.0dBc/Hz Phase Noise at 10MHz Offset and 190.3dBc/Hz Peak FoM in 65nm CMOS

The millimeter-wave (mm-wave) high-speed wireless communication has placed stringent requirements on the phase-noise performance of the local oscillators (LO), especially when a high-order modulation such as 1024-QAM is used. To meet the phase noise requirement, one can use a subharmonic oscillator followed by frequency multipliers to improve the phase noise performance [1]. However, the frequency multipliers and the necessary extra amplification stages consume a large chip area and power. On the other hand, mm-wave fundamental VCOs suffer from the Q drop as inductance becomes too small due to the inner-edge deconstructive coupling in single-turn inductors [2]. To overcome this problem, multicore technologies are used in mm-wave fundamental oscillators [2 – 6]. By coupling N cores together, the phase noise can be improved by 10log(N). At the same time, the inductance in each core can be large for the given phase-noise requirement, thus alleviating the small-inductor problem. The key to a multicore oscillator design is to effectively synchronize each oscillator core. The left top of Fig. 9.3.1 shows the schematic of the resistance-coupled multicore oscillator [3 – 5], where resistors are placed between the corresponding output nodes of each core. The resistance-coupling scheme is good for a small number of cores, such as 2 cores or 4 cores, where the output node of each core can be physically close to each other. In a many-core extension, as shown in the left-middle of Fig. 9.3.1, some of the coupling resistors stretch over a long distance, which increases their parasitic capacitance and contributes to tank mismatch. It also suffers from the trade-off between the lock range and parasitic capacitance. The right top of Fig. 9.3.1 shows the schematic of the proposed transformer-based mode-rejection-coupled multicore oscillator. In this scheme, the oscillator active core shares the transformer tank with its two adjacent cores, and isolation resistors are placed in the middle of gate coils. The resistor damps the Q of the transformer in the common mode, forcing the voltage signals at the two sides of the transformer to be differential, therefore synchronizing the oscillator cores. The transformer-based mode-rejection-coupled scheme has several advantages over the resistance-coupled scheme. First, the isolation resistors are transparent in the differential mode, therefore providing robust coupling without the parasitic capacitance penalty. Second, because the two sides of transformers are connected to two different active cores, they do not have to be physically close to each other, thus enabling the slab type inductors, which can achieve simultaneous small inductance and high Q as in [2]. Third, since the resistors are only placed at local-gate central taps, the transformer-based mode-rejection-coupled scheme is suitable for the many-core extension. Similar mode-rejection-coupled ideas have been used in [2, 6]. Single inductors, instead of transformers, are used in [2], which only applies to CMOS configuration due to the power-supply issue. Triple-coupled-transformers are used in [6], where the source coil is much shorter than the coils at gate and drain terminals, making it difficult to extend to more than 4 cores. In this work, a transformer-based mode-rejection-coupled many-core fundamental oscillator is proposed. A 16-core oscillator is prototyped in a 65nm CMOS process and achieves -136.0dBc/Hz phase noise at a 10MHz offset, 190.3dBc/Hz peak FoM at 10MHz, and a 53.6-to-60.2GHz frequency-tuning range.