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静电放电
电压
CMOS芯片
波形
电气工程
残余物
电子工程
工程类
计算机科学
算法
作者
В.А. Ващенко,Mirko Scholz,P. Jansen,Ronald C. Petersen,M. Natarajan,David Trémouilles,M. Sawada,T. Nakaei,T. Hasebe,M. ter Beek,G. Groeseneken
出处
期刊:Electrical Overstress/Electrostatic Discharge Symposium
日期:2006-09-01
卷期号:: 39-45
被引量:5
摘要
The residual voltage across the ESD snapback protection device after its turn-off is one of the key parameters that must be considered for efficient ESD protection design. Turn-off characteristics of various snapback devices (5VNMOS, 5V LVTSCR and 12V DeMOS-SCR), are analyzed with experimental data for the first time and it is demonstrated that the residual voltage after turn-off is a unique parameter and depends on the type of ESD device, its architecture and layout. The residual voltage after turn-off can vary in a wide range from holding voltage to DC breakdown voltage and is a function of the ESD pulse amplitude. The underlying physical mechanism causing the waveform behavior is discussed in detail.
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