A logarithmic response burst IRFPA ROIC with pixel level integration of memory

This paper presents a logarithmic response burst mode IRFPA ROIC with pixel level integration of BDI structure and memory cells. BDI structure provides stable bias for the detector, and converts detector current into logarithmic voltage fast. On-chip high speed video record is achieved by high speed sampling the logarithmic response voltage and storing it into the memory cells in order. A column level SAR ADC is used to convert the outputs of memory cells into digital code. The prototype chip with 64×64 pixels was designed and fabricated. Ultra-high speed video capturing at 1Mfps with 100 consecutive frames is successfully demonstrated.