Design of a Stable LDO Over the Full Load Range

With the development of electronic products in a lighter and more intelligent direction, low dropout voltage regulator, as a common power management chip, is widely used in many fields due to its small size, low noise and fast response. This paper propose a design methodology to improve the stability of a LDO regulators. Firstly, a buffer is inserted between the main operational amplifier and the gate of the regulator tube to reduce the frequency of the main pole. Secondly, a zero following the output pole is introduced to compensate the loop by using parallel AC feedback technology. As a proof of concept, a stable LDO is designed in this work. The LDO is based on the SMIC $0.18\mu \mathrm{m}~1.8\mathrm{V}\sim 40\mathrm{V}$ BCD M-EP process and is simulated in Candence. Simulation results show that the proposed method can be used to improve the stability of the loop. And the improvement on the stability is more obvious in the case of light load, where the phase margin is 60° higher than the case without the proposed method.