Ab-Initio Quantum Transport Simulation of Sub-1 nm Gate Length Monolayer and Bilayer WSe2 Transistors: Implications for Ultra-Scaled CMOS Technology

Ultrascaled sizes and symmetrical n- and p-type performance are the pursuit of next-generation field effect transistors (FETs). Although sub-1 nm gate length MoS2 n-FETs have been experimentally fabricated, the performance of such ultrashort p-type transition metal dichalcogenide transistors is still unknown. In this work, we study the transport properties of the WSe2 p-FETs with a gate length of 0.34 nm (the thickness of graphene) by ab initio quantum transport simulation. The optimized monolayer (ML) WSe2 transistor with a channel length shorter than 5 nm can satisfy the International Technology Roadmap for Semiconductors standard for high-performance (HP) devices with a high on-state current of 712 μA/μm. Due to changes in the band structure and degradation of gate control, the on-state current of the bilayer WSe2 transistor decreases by 40% compared to that of ML-FET. Moreover, we find that high-k dielectric layer helps to suppress the short channel effect with the same effective oxide thickness (EOT). This work provides a basis for advancing ultrascaled CMOS technology in the future.