PMOS逻辑
NMOS逻辑
寄生提取
薄脆饼
晶体管
材料科学
制作
过程(计算)
电子工程
过程集成
足迹
计算机科学
电气工程
工程类
光电子学
电压
病理
古生物学
工艺工程
操作系统
生物
医学
替代医学
作者
S. Subramanian,M. Reza Hosseini,T. Chiarella,Santonu Sarkar,P. Schuddinck,Boon Teik Chan,D. Radisic,G. Mannaert,Andriy Hikavyy,Erik Rosseel,Farid Sebaai,A. Peter,T. Hopf,P. Morin,S. Wang,K. Devriendt,Dmitry Batuk,Gerardo Martínez,A. Veloso,E. Dentoni Litta
标识
DOI:10.1109/vlsitechnology18217.2020.9265073
摘要
We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A monolithic CFET process is cost effective compared to a sequential CFET process. The small N/P separation in a monolithic CFET results in lower parasitics and higher performance gains. In this paper, using a CFET fabrication process flow, we demonstrate functional PMOS FinFET bottom devices and NMOS nanosheet FET top devices. Process development of all the critical modules to enable these devices are presented. Monolithic CFET integration scheme could enable the ultimate device footprint scaling required in future technology nodes.
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