Circuit optimization for minimisation of power consumption under delay constraint

We address the problem of optimization of VLSI circuits to minimize power consumption while meeting performance goals. We present a method of estimating power consumption of a basic or complex CMOS gate which takes the internal capacitances of the gate into account. This method is used to select an ordering of series-connected transistors found in CMOS gates to achieve lower power consumption. We describe a multipass algorithm which makes use of transistor reordering to optimize performance and power consumption of circuits and which has a linear time complexity per pass. The algorithm has been benchmarked on several large examples and the results are presented.