与非门
缩放比例
太比特
计算机科学
光电子学
材料科学
逻辑门
算法
波长
几何学
数学
波分复用
作者
S. Fransen,Kherim Willems,Harold Philipsen,Devin Verreck,W. Van Roy,Olivier Henry,A. Arreghini,G. Van den bosch,A. Furnémont,M. Rosmeulen
标识
DOI:10.1109/ted.2022.3162176
摘要
We propose a storage memory device that enables bit densities of >1 Tbit/mm 2 based on the electro- deposition and electrodissolution of multilayered metal stacks in deep nanometer-sized wells. This device addresses the challenge of bit density scaling slowdown expected for 3-D NAND flash beyond 2030. We describe in detail the operating principles and discuss the response time, bandwidth, retention, and cycling endurance requirements for the device to be viable. As a proof-of-principle, we provide a first demonstration of the write/read (W/R) mechanism on millimeter- and micrometer-sized electrodes and show the device’s potential for reaching very high bit densities. To evaluate how the response time scales for the envisioned nanometer-sized electrodes, we derive simple analytical expressions based on finite element simulations that relate the well depth, radius, and electrolyte composition to the deposition/dissolution rate.
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