Electrostatic-Induced Particle Behavior Simulation Framework in Cleaning Process: Interaction between Solid-Liquid Interfaces

A comprehensive understanding of electrostatic-induced particle trapping during semiconductor wafer cleaning processes is paramount for enhancing device yield and performance. In this study, we employed a three-dimensional (3D) simulation framework to systematically analyze the interplay between electrical field strength, particle size, and electrostatic forces on particle trapping phenomena and defect pattern formation. Our findings revealed that increased electrical field strength and decreased particle size contribute to a higher probability of particle trapping and the emergence of distinct defect patterns. Based on these insights, we propose an optimization strategy to improve the cleaning process efficiency and minimize particle trapping, ultimately advancing the yield and performance of semiconductor devices.