High voltage time-dependent dielectric breakdown in stacked intermetal dielectrics

Stacked intermetal dielectrics grown by a Plasma Enhanced Chemical Vapor Deposition (PECVD) technique are widely used as a capacitive voltage divider to integrate low and high power ICs. The voltage-divider must sustain multi-kV operation for years in harsh (hot and humid) environment. Therefore, a fundamental understanding of the degradation mechanisms of the dielectric is an essential prerequisite for its safe operation. While the reliability of PECVD oxides has been extensively studied, the reliability of stacked oxides, with numerous chemically and mechanically polished (CMP) interfaces, is not fully understood. In fact, the dielectric reliability would differ dramatically if the stack behaves as a single thick capacitor vs. if CMP-damaged interfaces render the stack into a set of capacitors connected in series. In this paper, we use a wide range of the stacked intermetal dielectric (= 1~20 μm) to study their Time-dependent dielectric breakdown (TDDB) degradation mechanism. Our results demonstrate that the stacked dielectric do behave as a single unit, but unlike conventional TDDB in submicron gate oxide, the TDDB of stacked dielectrics is determined by impact ionization and charge trapping. We explored the degradation mechanism in detail through experiments and simulation; the results are embedded in an acceleration model that can be used to predict TDDB lifetime at arbitrary operating conditions.