移植
计算机科学
静态随机存取存储器
异步通信
稳健性(进化)
嵌入式系统
电子工程
计算机硬件
工程类
电信
生物化学
化学
软件
基因
程序设计语言
作者
Jonathan Dama,Andrew Lines
标识
DOI:10.1109/async.2009.23
摘要
This paper details the design of > 1 GHz pipelined asynchronous SRAMs in TSMC's 65 nm GP process. We show how targeted timing assumptions improve an otherwise quasi delay-insensitive (QDI) design. The speed, area, and power of our SRAMs are compared to commercially available synchronous SRAMs in the same technology. We also present novel techniques for implementing large pseudo dual-ported memories that support simultaneous reads and writes. The most sophisticated of three designs yields a fully provisioned dual-ported memory using multiple single-ported banks connected by dual-ported buses, plus a small side-band memory to avoid bank conflicts. We discuss our solutions for manufacturing defects, soft-errors, and analog robustness with attention to .advantages and challenges of our asynchronous methodology. Laboratory measurements of a test-chip demonstrate correct functionality at speeds well over a GHz. Our single-ported SRAM designs are larger but faster than the alternate synchronous designs, while our novel dual-ported implementations can be both smaller and much faster. These technology advantages lead directly to competitive advantages for our future commercial products.
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