Fast Constraints Tuning via Transfer Learning and Multi-Objective Optimization

As the complexity of very-large-scale integration (VLSI) increases, empirically determining the design constraints necessary to achieve the optimal performance, power, and area (PPA) within the electronic design automation (EDA) workflow becomes more challenging. Design space exploration is capable of effectively and automatically identifying the design constraints required to attain the optimal PPA in VLSI designs. However, the absence of prior knowledge can lead to less efficient explorations. This paper proposes a novel fast constraint tuning framework via transfer learning and multi-objective Bayesian optimization (MOBO) to find the optimal design constraints. Firstly, we introduce transfer learning into multi-objective Bayesian optimization by Gaussian Copula and transform the PPA data into residual observations. We propose to transfer the prior information of the implemented technologies to the advanced technology to optimize the parameter design space under the advanced technology. Secondly, we propose Gaussian process regression with an auto-encoder-based deep kernel as a surrogate model in MOBO. The auto-encoder-based deep kernel can extract more input features to make the surrogate model more precise. We employ the batch uncertainty-aware search acquisition function to improve exploration efficiency. Using this surrogate model and this acquisition function in MOBO can reduce the amount that EDA tools need to run. The average EDA tools running times of the proposed model is 204, and the average ADRS is 0.0373. Compared to state-of-the-art approaches, experiments on a CPU design reveal that a higher-quality Pareto frontier can be provided with a shorter running time.