A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing

A SAR ADC comprises only a T/H, a comparator, SAR logics, and a capacitive DAC, thus exhibiting a power-efficient topology with low complexity, low power consumption, and friendly process technology scaling down. Consequently, it has a wide utilization in high-speed applications (like in time-interleaved SARs). Previous works improved the 1b/cycle topology to speed up SAR ADC conversions, leading to multi-bit/cycle [1] and N-bits N-comparators [2] structures. Compared with the above architectures, the conventional 1b/cycle topology still has apparent advantages related to low complexity, less parasitic, and less offset problems. Therefore, currently, the 1b/cycle is still the first choice for the majority of high-speed TI SAR ADCs [3]. The popularization of the high-speed SAR ADC with redundant bit structures can lead to a very short settling time required for the DACs [4]. However, the speed of the SAR is still a bottleneck, especially limited by the digital SAR logic [2].