Jitter analysis and modeling of a 10 Gbit/s SerDes CDR and jitter attenuation PLL

Abstract Jitter analysis and a linear model is proposed in this paper which predicts the characteristics of serial-deserial (SerDes) clock and data recovery circuit, and the characteristics include jitter transfer, jitter tolerance and jitter generation are particularly analyzed. The simulation results of the clock data recovery (CDR) model show that the jitter specifications exceed the mask of ITU-T optical transport network (OTN) G.8251 recommendations. The whole systems are validated by 9.95–11.5 Gbit/s CDR and the jitter attenuation phase locked loops (PLL) circuits using TSMC 65 nm CMOS technology.