CMOS芯片
异步通信
逐次逼近ADC
以太网
电子工程
有效位数
计算机科学
绝缘体上的硅
比较器
物理
工程类
电气工程
电压
计算机硬件
电信
光电子学
硅
作者
Lukas Kull,Thomas Toifl,M. Schmatz,Pier Andrea Francese,Christian Menolfi,Matthias Braendli,Marcel Kossel,Thomas Morf,Tom Løgstrup Andersen,Yusuf Leblebici
出处
期刊:International Solid-State Circuits Conference
日期:2014-02-01
被引量:68
标识
DOI:10.1109/isscc.2014.6757477
摘要
Forthcoming optical communication standards such as ITU OTU-4 and 100/400Gb/s Ethernet require ADCs with more than 50GS/s and at least 5 ENOB to enable complex equalization in the digital domain. SAR ADCs and interleaved ADCs made impressive progress in recent years. First CMOS ADCs with at least 6b and conversion rates exceeding 20GS/s were presented, proving that interleaved SAR ADCs are an optimal choice for high-speed ADCs with moderate resolution. We present an interleaved CMOS ADC architecture based on an asynchronous redundant SAR ADC core element. It was measured up to a sampling rate of 100GS/s and can be operated from a single supply voltage. At 90GS/s, the measured SNDR stays above 36.0dB SNDR up to 6.1GHz and 33.0dB up to 19.9GHz input frequency while consuming 667mW. The ADC is implemented in 32nm digital SOI CMOS and occupies 0.45mm 2 .
科研通智能强力驱动
Strongly Powered by AbleSci AI