A 256 bit Nonvolatile Static Random Access Memory with MNOS Memory Transistors

A p-channel 256 bit nonvolatile static RAM which is essentially free from any limitation to the memory cycles is developed by means of a new concept of a nonvolatile flip-flop. The logical organization is 64 word × 4 bit. The memory can be operated as a static memory with access time of 400 ns and cycle time of 1 µs under a stable power supply, and as a non-volatile memory with data retentivity of about one year. Nonvolatile writing to the MNOS transistors is done only when the power supply is turned off and on. The allowable number of on/off cycles can exceed 105 cycles under normal operating conditions. Power dissipation as a static RAM is less than 600 mW and that as a nonvolatile memory is zero. Both inputs and outputs are TTL compatible except for the signal to the gate of MNOS transistors.