比较器
最低有效位
解码方法
CMOS芯片
偏移量(计算机科学)
电子工程
计算机科学
误码率
电压
电气工程
工程类
算法
程序设计语言
操作系统
作者
Jincheol Sim,Hyunsu Park,Yoonjae Choi,Jong-Hyuk Choi,Youngwook Kwon,Chulwoo Kim
出处
期刊:IEEE Transactions on Circuits and Systems I-regular Papers
[Institute of Electrical and Electronics Engineers]
日期:2023-02-14
卷期号:70 (5): 1907-1916
被引量:1
标识
DOI:10.1109/tcsi.2023.3241929
摘要
This study presents a wireline pulse amplitude modulation-4 (PAM-4) receiver using the least significant bit (LSB) decoding method that uses the offset of comparators. The proposed LSB decoding method can generate the same output as that of a conventional comparator by effectively adding the desired offset voltage to only one of the differential PAM-4 signals. Because the proposed decoding method replaces a 4-input comparator with a 2-input comparator, it can improve the bit error rate (BER) performance of the LSB by as much as the most significant bit (MSB). The predetermined offset is useful not only for LSB decoding but also for the direct decision feedback equalizer (DFE) operation. The differential amplitude and common-mode voltage (VCM) of the PAM-4 signal vary owing to the direct DFE tap coefficient. The modified comparator can generate an appropriate offset voltage without an adaptation loop or a VCM compensator although the PAM-4 signals are changed depending on the DFE tap coefficient. A prototype is fabricated using 28-nm CMOS technology and tested using a 10.29 dB channel attenuation at 10 GHz. The maximum data rate is 40 Gb/s, and the power efficiency and area of the proposed architecture are 1.58 pJ/bit and 0.039 mm2, respectively.
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